PTN3355

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Product data sheet

Rev. 3.1 — 4 November 2016

20 of 37

NXP Semiconductors

PTN3355

Low power DP to VGA adapter with integrated 1 : 2 VGA switch

13.2 DisplayPort receiver main link

[1]

Ref. 1 supersedes in case of any mismatch of specification items.

[2]

Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported.

[3]

Informative; refer to Figure 8 for definition of differential voltage.

[4]

Common mode voltage is equal to Vbias_RX voltage.

[5]

Total drive current of the input bias circuit when it is shorted to its ground.

[6]

The measurements are always taken with PRBS7 test signal. Minimum CDR closed loop tracking bandwidth at the receiver when the

input is a PRBS7 pattern.

Table 15.

DisplayPort receiver main link characteristics[1]

Over operating free-air temperature range, unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

UI

unit interval

for high bit rate

(2.7 Gbit/s per lane)

-370

-ps

for low bit rate

(1.62 Gbit/s per lane)

-617

-ps

f

DOWN_SPREAD

link clock down spreading

[2] 0.0-

0.5%

VRX_DIFFp-p

differential input peak-to-peak

voltage

at RX package pins

for high bit rate

[3] 120

--mV

for reduced bit rate

[3] 40

--mV

VRX_DC_CM

RX DC common mode voltage

[4] 0-

2.0

V

IRX_SHORT

RX short-circuit current limit

[5] --50

mA

CRX

AC coupling capacitor

on DP Main Link and

AUX inputs

75

-

200

nF

fRX_TRACK_BW_HBR

jitter closed loop tracking bandwidth

(High Bit Rate)

[6] 10

-

20

MHz

fRX_TRACK_BW_RBR

jitter closed loop tracking bandwidth

(Reduced Bit Rate)

[6] 5.4

-

20

MHz

pre-emphasis = 20Log(VDIFF_PRE /VDIFF)

Fig 8.

Definitions of pre-emphasis and differential voltage

002aaf363

VD+

VCM

VD−

VDIFF_PRE VDIFF