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FS23 Scheda tecnica(PDF) 122 Page - NXP Semiconductors

Il numero della parte FS23
Spiegazioni elettronici  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS23 Scheda tecnica(HTML) 122 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
Bit
Symbol
Description
Configure V3 state in LPON mode
0 Follow the power-down slot configuration
1 Keep V3 ON in LPON if V3 was already ON in Normal mode
2
V3ON_LPON
POR
Request to disable V2
0 No effect (Regulator remains in its current state)
1 Request to disable V2
3
V2DIS
POR, self-clear
Request to enable V2
0 No effect (Regulator remains in its current state)
1 Request to enable V2
4
V2EN
POR, self-clear
Configure V2 state in LPON mode
0 Follow the power down slot configuration
1 Keep V2 ON in LPON if V2 was already ON in Normal mode
5
V2ON_LPON
POR
Select BUCK slew rate when the high-side turns ON
000 HS rising slew rate is 20 ns (for 450 KHz only)
001 HS rising slew rate is 20 ns (for 450 KHz only)
010 HS rising slew rate is 15 ns (for 450 KHz only)
011 HS rising slew rate is 10 ns
100 HS rising slew rate is 6.3 ns
101 HS rising slew rate is 5 ns
110 HS rising slew rate is 3 ns
111 HS rising slew rate is 2 ns
8 to 10
BUCK_SRHSON
OTP fuse load
Select BUCK slew rate when the high-side turns OFF
00 HS falling slew rate is 20 ns (for 450 KHz only)
01 HS falling slew rate is 15 ns (for 450 KHz only)
10 HS falling slew rate is 10 ns
11 HS falling slew rate is 5 ns
11 to 12
BUCK_SRHSOFF
OTP fuse load
Table 88. M_REG_CTRL register bit description...continued
22.8 M_REG_FLG
Bit
15
14
13
12
11
10
9
8
Write[1]
V0UV_I
V0OV_I
V1TWARN_I
V1TSD_I
V2TSD_I
V3TSD_I
V2OL_I
V1UV_I
Read
V0UV_I
V0OV_I
V1TWARN_I
V1TSD_I
V2TSD_I
V3TSD_I
V2OL_I
V1UV_I
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Write[1]
V2UV_I
V3UV_I
V1OV_I
V2OV_I
V3OV_I
V1OC_I
V2OC_I
V3OC_I
Read
V2UV_I
V3UV_I
V1OV_I
V2OV_I
V3OV_I
V1OC_I
V2OC_I
V3OC_I
Reset
0
0
0
0
0
0
0
0
Table 89. M_REG_FLG register bit allocation
[1]
Write 1 in a flag to clear it.
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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