R34DS0017EU0104 Rev.1.04

Page 32

Jan 31, 2025

ISL73041SEH Datasheet

7.

PCB Layout

7.1

Layout Guidelines

It is crucial to consider and follow the general printed circuit board layout guidelines to maximize the performance

of the ISL73041SEH half-bridge driver and the power GaN FETs it is driving.

▪ Place low ESR X7R grade or better ceramic capacitors for high-frequency decoupling as close to the package

pins as possible. These include the capacitors between VDD-SGND, AVCC-SGND, PVCC-PGND, and BOOT-

PHS.

▪ Place the RDU and RDL dead-time control resistors close to their respective pins and connect them to SGND

through the PCB GND plane.

▪ Connect the four bottom EPAD of the package to the top layer GND plane of the PCB. To further improve

thermal performance, place at least four vias in the GND plane under the package EPAD to another internal

GND plane to dissipate heat.

▪ Place the ISL73041SEH close to the half-bridge power GaN FET to minimize trace inductance and high current

loop area between the driver output and the GaN FET gate.

▪ Connect the PGND pin and the low-side FET source commonly through the same PCB ground plane as the

SGND PAD. Alternatively, connect the PGND pin to the low-side FET source-sense terminal if it is available.

Arrange the components and route the trace to keep this PGND inductance low.

Figure 51. Connection for Dual Low-Side Driver

PWM

BOOT

UGH

UGL

PHS

LGH

LGL

PVCC

PGND

VDD

RDU

RDL

FB

EN

PVCC

FLTb

Level Shift &

Boot UVLO

PVCC

UVLO

Leading

Delay

Leading

Delay

Matching

Delay

PVCC

LDO

OTP

AVCC

LDO

AVCC

Low-Side

Logic

High-Side

Logic

SGND

Switch

Control

PWM

PHS

SGND

PGND

1kΩ

500Ω

EN

AVCC

UVLO

SGND

DR_EN

DR_EN

DR_EN

VDD

UVLO

AVCC UV

VDD UV

VDD UV

VDD UV

VDD UV

HI

LOW

Tri-Level

Comparator

SGND

AVCC

225kΩ

150kΩ

VREF

In Phase

with PWM

Inverterd

with PWM