R34DS0017EU0104 Rev.1.04

Page 24

Jan 31, 2025

ISL73041SEH Datasheet

5.

Functional Description

5.1

Half-Bridge Driver

The ISL73041SEH is a high-frequency 12V Half-bridge driver for enhancement mode N-type GaN FETs or logic

level NMOS FETs. High peak drive current and fast propagation delay time with tight matching allow driving low

rDS(ON) FETs in high-frequency DC/DC and motor control applications. With an integrated programmable gate

drive voltage, high-side level shifter, and bootstrap switch, only a few external components are needed to drive

N-type GaN or MOS FETs in a half-bridge configuration.

5.2

GaN/MOS FET Gate Drive Supply

A programmable gate drive supply from 4.5V to 5.5V allows users to optimize the gate voltage for different GaN

FETs and logic-level MOSFETs. Renesas GaN FETs recommend a nominal 4.5V gate drive voltage. Other GaN

FET vendors can tolerate up to 5.5V. The programmable function allows users to optimize gate drive voltage for

low rDS(ON) and GaN FET reliability.

5.3

PWM Input

The PWM pin features a tri-level input for controlling the driver outputs.

▪ PWM = Low for low-side FET on

▪ PWM = High for the high-side FET on

▪ When PWM is at mid-level, both drivers are off.

A PWM input half-bridge driver inherently prevents one type of bridge shoot-through by not allowing the input logic

to command both the high-side and low-side drivers simultaneously. The tri-level input allows the half-bridge to be

in a high-impedance state during soft-start or hiccup of a PWM controller or for phase dropping in multi-phase

regulators. The ISL73041SEH GaN FET Driver is designed to interface with the ISL73847SEH 2-phase PWM

Controller.

5.4

Dead Time Control

Because a PWM input driver controls both drivers in a complimentary on/off state, dead time control is needed to

prevent shoot-through at the half-bridge FET gates. The ISL73041SEH integrates independent high-side and low-

side dead time control on the RDU and RDL pins for delaying the rising edge gate turn-on from the falling edge of

gate turn-off. The rising edge dead time delay is programmable from 6.5ns to 50ns with a single resistor on RDU

and RDL to ground.

5.5

Driver Output Architecture

The ISL73041SEH half-bridge driver incorporates a 2-stage output for high peak drive currents while minimizing

quiescent current. The driver turn-on circuit includes a P-channel transistor and a transient N-channel transistor.

When the driver output is low, the N-channel has maximum drive capability to assist in the rise time of the turn-on.

As the output reaches near the high level, the N-channel no longer provides drive strength and is only held on by

the P-channel. Conversely, the driver turn-off circuit includes an N-channel transistor and a transient P-channel

transistor. When the driver output is high, the P-channel has maximum drive capability to assist in the fall time of

the turn-off. As the output reaches near the low level, the P-channel no longer provides drive strength and is only

held on by the N-channel.