LM98640CVAL datasheet(21/55 Pages) TI2

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LM98640QML-SP

CCD Timing

Analog

Front End

Sensor Drivers

Image

Processor/

ASIC

Data Output

SPI

CCD/CIS Sensor

LM98640QML-SP

www.ti.com

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

Product Folder Links: LM98640QML-SP

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Functional Block Diagram (continued)

Figure 14. Typical CCD System

7.3 Feature Description

7.3.1 Input Sampling Modes

The LM98640QML-SP provides two input sampling modes, Sample & Hold mode and Correlated Double Sample

(CDS) mode. The following sections describe these two input sampling modes.

7.3.1.1 Sample & Hold Mode

In Sample/Hold mode, a Video Level signal and a Reference Level signal need to be presented to the

LM98640QML-SP. The Reference Level signal must be connected to the OSX+ pin, and the Video Level signal

connected to the OSX- pin. The output code will then be OSX+ minus OSX-, or the difference between the

Reference Level and Video Level. A minimum code represents zero deviation between the Reference and Video

Levels and a maximum code represents a 2-V deviation between the Reference and Video Levels with CDS and

PGA gains of 1x.

The Reference Level signal can be either an external signal from the image sensor, or the VCLP pin can be

externally connected to the OSX+ pin. In order to fully utilize the range of the input circuitry it is desirable to

cause the Black Level signal voltage to be as close to the Reference Level voltage as possible, resulting in a

near zero scale output for Black Level pixels. The LM98640QML-SP provides several methods for ensuring the

Black Level signal and Reference Level are matched, these are described in the Input Bias and Clamping

section.

To place the LM98640QML-SP in Sample & Hold Mode from power up, first write the baseline configuration to

the registers as shown in Table 5. This configuration has Sample & Hold mode enabled by default. Next, the

SAMPLE pulse must be properly positioned over the input signal using the CLAMP/SAMPLE Adjust.

7.3.1.1.1

Sample & Hold Mode CLAMP/SAMPLE Adjust

For accurate sampling of the input signals the LM98640QML-SP allows for full adjustment of the internal

SAMPLE pulse to align it to the proper positions over the input signal. In Sample & Hold mode the SAMPLE

pulse should be placed over the pixel output period of the image sensor. Only the Sample Start and Sample End

Registers (0x22,0x23) need to be configured, the Clamp Start and Clamp End Registers (0x20,0x21) are not

valid in Sample & Hold Mode. Internally the input clock is divided into 64 edges per clock period, the Sample

Start and Sample End Registers correspond to the internal edge number the SAMPLE pulse will start and end.

To adjust the SAMPLE pulse, first send the CLAMP and SAMPLE signals to the DTM pins by writing 10 to

bits[4:3] of the Clock Monitor Register (0x09). This will allow the user to observe the SAMPLE pulse on pin DTM1

along with the image sensor output using an oscilloscope. Then, using the Sample Start and End Registers,

adjust the SAMPLE pulse to align it over the Video Level portion of the image sensor output. To allow for settling

and to reduce noise, the SAMPLE pulse should be made as wide as possible and fill the entire Video Level

portion of the input signal.

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