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LM98640CVAL Scheda tecnica(PDF) 12 Page - Texas Instruments |
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LM98640CVAL Scheda tecnica(HTML) 12 Page - Texas Instruments |
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12 / 55 page ![]() 12 LM98640QML-SP SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 www.ti.com Product Folder Links: LM98640QML-SP Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated LM98640QML-SP Electrical Characteristics (1)(2) (continued) The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 40 MHz unless otherwise specified. PARAMETER TEST CONDITIONS NOTES SUB- GROUPS MIN TYP(3) MAX UNIT (4) Dynamic Power Supply Rejection Ratio is performed by injecting a 200-mVpp sine wave ac coupled to the analog supply pin. The LM98640QML-SP inputs are left floating in CDS mode and an FFT is captured. The spur ensured by the injected signal is recorded. (5) This parameter is ensured by design and/or characterization and is not tested. PSRR Dynamic Power Supply Rejection Ratio CDS Gain = 1x PGA Gain = 1x 200 mVpp, 200 KHz See(4) –72.3 dB 200 mVpp, 500 KHz –72 200 mVpp, 1 MHz –71 200 mVpp, 1.5 MHz –68 200 mVpp, 2 MHz –66 INTERNAL REFERENCE SPECIFICATIONS VREFBG Reference Voltage See(5) 1.218 V Reference Tolerance (chip to chip) See(5) ±2% RREFBG Reference Impedance See(5) 20 kΩ VREFTC Temperature Coefficient 25°C to 125°C 80 ppm/ °C –55°C to 25°C 50 INPUT SAMPLING CIRCUIT SPECIFICATIONS VIN Input Voltage Level CDS Gain = 1x, PGA Gain = 1x 1, 2, 3 2 Vp-p CDS Gain = 2x, PGA Gain= 1 x 1 CDS Gain = 1x, PGA Gain = 0.7x 2.85 VRESET Reset Feed Through 500 mV IIN_SH Sample and Hold Mode Input Leakage Current CDS Gain = 1x See(5) 384 μA OSX = VDD33 (OSX = VSS) CDS Gain = 2x See(5) –475 µA OSX = VDD33 (OSX = VSS) CSH Sample/Hold Mode CDS Gain = 1x See(5) 4 pF Equivalent Input Capacitance (see Figure 20) CDS Gain = 2x See(5) 8 pF IIN_CDS CDS Mode OSX = VDD33 (OSX = VSS) See(5) 300 nA Input Leakage Current RCLPIN CLPIN Switch Resistance See(5) 16 Ω (OSX to VCLP Node in Figure 17) |
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