Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

LM98640CVAL Scheda tecnica(PDF) 12 Page - Texas Instruments

Il numero della parte LM98640CVAL
Spiegazioni elettronici  LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
PDF  55 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments

LM98640CVAL Scheda tecnica(HTML) 12 Page - Texas Instruments

Back Button LM98640CVAL Datasheet HTML 8Page - Texas Instruments LM98640CVAL Datasheet HTML 9Page - Texas Instruments LM98640CVAL Datasheet HTML 10Page - Texas Instruments LM98640CVAL Datasheet HTML 11Page - Texas Instruments LM98640CVAL Datasheet HTML 12Page - Texas Instruments LM98640CVAL Datasheet HTML 13Page - Texas Instruments LM98640CVAL Datasheet HTML 14Page - Texas Instruments LM98640CVAL Datasheet HTML 15Page - Texas Instruments LM98640CVAL Datasheet HTML 16Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 55 page
background image
12
LM98640QML-SP
SNAS461G – MAY 2010 – REVISED NOVEMBER 2018
www.ti.com
Product Folder Links: LM98640QML-SP
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
LM98640QML-SP Electrical Characteristics
(1)(2) (continued)
The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 40 MHz unless otherwise
specified.
PARAMETER
TEST CONDITIONS
NOTES
SUB-
GROUPS
MIN TYP(3)
MAX UNIT
(4)
Dynamic Power Supply Rejection Ratio is performed by injecting a 200-mVpp sine wave ac coupled to the analog supply pin. The
LM98640QML-SP inputs are left floating in CDS mode and an FFT is captured. The spur ensured by the injected signal is recorded.
(5)
This parameter is ensured by design and/or characterization and is not tested.
PSRR
Dynamic Power Supply Rejection
Ratio
CDS Gain = 1x
PGA Gain = 1x
200 mVpp, 200 KHz
See(4)
–72.3
dB
200 mVpp, 500 KHz
–72
200 mVpp, 1 MHz
–71
200 mVpp, 1.5 MHz
–68
200 mVpp, 2 MHz
–66
INTERNAL REFERENCE SPECIFICATIONS
VREFBG
Reference Voltage
See(5)
1.218
V
Reference Tolerance
(chip to chip)
See(5)
±2%
RREFBG
Reference Impedance
See(5)
20
VREFTC
Temperature Coefficient
25°C to 125°C
80
ppm/
°C
–55°C to 25°C
50
INPUT SAMPLING CIRCUIT SPECIFICATIONS
VIN
Input Voltage Level
CDS Gain = 1x, PGA Gain =
1x
1, 2, 3
2
Vp-p
CDS Gain = 2x, PGA Gain= 1
x
1
CDS Gain = 1x, PGA Gain =
0.7x
2.85
VRESET
Reset Feed Through
500
mV
IIN_SH
Sample and Hold Mode
Input Leakage Current
CDS Gain = 1x
See(5)
384
μA
OSX = VDD33 (OSX = VSS)
CDS Gain = 2x
See(5)
–475
µA
OSX = VDD33 (OSX = VSS)
CSH
Sample/Hold Mode
CDS Gain = 1x
See(5)
4
pF
Equivalent Input Capacitance
(see Figure 20)
CDS Gain = 2x
See(5)
8
pF
IIN_CDS
CDS Mode
OSX = VDD33 (OSX = VSS)
See(5)
300
nA
Input Leakage Current
RCLPIN
CLPIN Switch Resistance
See(5)
16
Ω
(OSX to VCLP Node in Figure 17)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com