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LM98640CVAL Scheda tecnica(PDF) 36 Page - Texas Instruments

Il numero della parte LM98640CVAL
Spiegazioni elettronici  LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
PDF  55 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments

LM98640CVAL Scheda tecnica(HTML) 36 Page - Texas Instruments

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background image
tOD
tIS
tIH
tSCSEN
tSENW
tSENSC
SCLK
SEN
tHZ
SDI
R/W
0
A5
A4
A3
A2
A1
A0
DI
[7]
DI
[6]
1
0
A5
A4
A3
A2
A1
A0
DI
[7]
DI
[6]
DI
[5]
DI
[4]
DI
[3]
DI
[2]
DI
[1]
DI
[0]
(R)
SDO
X
X
X
X
X
X
X
X
DO
[7]
DO
[6]
DO
[5]
DO
[4]
DO
[3]
DO
[2]
DO
[1]
DO
[0]
36
LM98640QML-SP
SNAS461G – MAY 2010 – REVISED NOVEMBER 2018
www.ti.com
Product Folder Links: LM98640QML-SP
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Programming (continued)
7.5.4 Serial Interface Timing Details
Figure 28. Serial Interface Specification Diagram
7.6 Register Maps
Registers need to be written with baseline values after power-up to place part in a valid state.
Table 5. Configuration Registers
ADDRES
S
(BINARY)
REGISTER TITLE
(MNEMONIC)
BASELINE
(BINARY)
REGISTER and BIT DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANALOG CONFIGURATION
00 0000
Main Configuration
0000 0100
Not Used
Coarse DAC
Enable
Fine DAC
Enable
Reserved
CLPIN Gating
Enable
CDS Gain
Enable
Reserved
CDS Enable
00 0001
Powerdown Control
0000 0000
Master
Powerdown
VCLP
Powerdown
Ch2 Ref Buf
Powerdown
Ch1 Ref Buf
Powerdown
Ch2 PGA
Powerdown
Ch1 PGA
Powerdown
Ch2 ADC
Powerdown
Ch1 ADC
Powerdown
00 0010
PGA Power Trimming
0010 0100
Reserved
PGA Stage 2 Bias Current Trimming
PGA Stage 1 Bias Current Trimming
00 0011
ADC Power Trimming
0101 1011
Reserved
ADC Current Trimming 2
ADC Current Trimming 1
00 0100
VCLP Control
0111 0100
Not Used
Buffer Enable
VCLP Enable
VCLP Voltage Level
00 0101
LVDS Output Modes
0000 1110
Clear
Reserved
Reserved
Reserved
Quad Lane
Enable
LVDS Enable
LVDS Control
00 0110
Sample & Hold
1000 0001
S/H Enable
Not Used
Ref Buf Power Level
Reserved
00 0111
Status
0000 0000
Not Used
False Lock
00 1000
Reserved
0000 0000
Reserved
00 1001
Clock Monitor
0000 0000
Not Used
Enable/Select
Not Used
00 1010
Reserved
0000 0000
Not Used
00 1011
Reserved
0000 0000
Not Used
00 1100
Reserved
0000 0000
Not Used
00 1101
Reserved
0000 0000
Not Used
00 1110
Reserved
0000 0000
Not Used
00 1111
Reserved
0000 0000
Not Used
GAIN & OFFSET DAC CONFIGURATION
01 0000
CDAC1
0000 0000
Not Used
Offset bit 8
01 0001
CDAC1
1111 1111
Offset Value bits 7:0
01 0010
FDAC1
0000 0000
Not Used
Offset bit 8
01 0011
FDAC1
1111 1111
Offset Value bits 7:0
01 0100
Reserved
0000 0000
Not Used
01 0101
PGA1
0110 0001
PGA Gain Value
01 0110
Reserved
0000 0000
Not Used
01 0111
Reserved
0000 0000
Not Used
01 1000
CDAC2
0000 0000
Not Used
Offset Bit 8
01 1001
CDAC2
1111 1111
Offset Value bits 7:0
01 1010
FDAC2
0000 0000
Not Used
Offset Bit 8
01 1011
FDAC2
1111 1111
Offset Value bits 7:0



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