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LM98640CVAL Scheda tecnica(PDF) 37 Page - Texas Instruments

Il numero della parte LM98640CVAL
Spiegazioni elettronici  LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
PDF  55 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments

LM98640CVAL Scheda tecnica(HTML) 37 Page - Texas Instruments

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LM98640QML-SP
www.ti.com
SNAS461G – MAY 2010 – REVISED NOVEMBER 2018
Product Folder Links: LM98640QML-SP
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Register Maps (continued)
Table 5. Configuration Registers (continued)
ADDRES
S
(BINARY)
REGISTER TITLE
(MNEMONIC)
BASELINE
(BINARY)
REGISTER and BIT DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01 1100
PGA2
0110 0001
PGA Gain Value
01 1101
Reserved
0000 0000
Not Used
01 1110
Reserved
0000 0000
Not Used
01 1111
Reserved
0000 0000
Not Used
TIMING CONFIGURATION
10 0000
Clamp Start
0000 1000
Not Used
Clamp Start Index
10 0001
Clamp End
0001 1100
Not Used
Clamp End Index
10 0010
Sample Start
0010 1000
Not Used
Sample Start Index
10 0011
Sample End
0011 1100
Not Used
Sample End Index
10 0100
Reserved
0011 0100
Reserved
10 0101
INCLK Range
0000 0010
Not Used
INCLK Range
Not Used
Reserved
10 0110
Reserved
0000 0000
Not Used
10 0111
Reserved
0000 0000
Not Used
10 1000
DLL Configuration
0000 1111
Reserved
DLL Reset
10 1001
Reserved
0000 0000
Not Used
10 1010
Reserved
0000 0000
Not Used
10 1011
Reserved
0000 0000
Not Used
10 1100
Reserved
0000 0000
Not Used
10 1101
Reserved
0000 0000
Not Used
10 1110
Reserved
0000 0000
Not Used
10 1111
Reserved
0000 0000
Not Used
DIGITAL CONFIGURATION REGISTERS
11 0000
Test Pattern Start
0000 0000
Start Upper Bits
11 0001
Test Pattern Start
0000 0000
Start Lower Bits
11 0010
Test Pattern Width
0000 0000
Width Upper Bits
11 0011
Test Pattern Width
0000 0000
Width Lower Bits
11 0100
Test Pattern Control
0000 0000
Pattern
Enable
Pattern Mode
Pseudo
Random
Enable
Seed Enable
Pattern Output Channel
11 0101
Test Pattern Pitch
0000 0000
Test Pattern Pitch
11 0110
Test Pattern Step
0000 0000
Test Pattern Step Code
11 0111
Test Pattern Channel
Offset
0000 0000
Not Used
Test Pattern Channel Offset
11 1000
Test Pattern Value
0000 0000
Pattern Upper Bits
11 1001
Test Pattern Value
0000 0000
Pattern Lower Bits
11 1010
Reserved
0000 0000
Not Used
11 1011
Reserved
0000 0000
Not Used
11 1100
Digital Configuration
0000 0000
Not Used
Auto Read
11 1101
Test & Scan Control
0000 0000
Not Used
Pattern Voting
Enable
U-Wire Voting
Enable
Not Used
Test Reset
Test Mode
Not Used
11 1110
Device ID
0100 1000
Device Revision ID. Engineering samples might be x01 or x47.
11 1111
Reserved
0000 0000
Not Used



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