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LM98640CVAL Scheda tecnica(PDF) 31 Page - Texas Instruments

Il numero della parte LM98640CVAL
Spiegazioni elettronici  LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output
PDF  55 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments

LM98640CVAL Scheda tecnica(HTML) 31 Page - Texas Instruments

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INCLK
TXFRM
TXOUT1
TXOUT2
TXCLK
DB13
TXOUT0
TXOUT3
(CH1 MSB)
(CH1 LSB)
DB12
DB11
DB10
DB9
DB8
DB7
(CH2 MSB)
(CH2 LSB)
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB13
DB12
DB11
DB13
DB12
DB11
DB6
DB5
DB4
DB6
DB5
DB4
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Odd Output
Tag
Even Output
Tag
tQSR
tQHF
tDOD
INCLK
TXFRM
TXOUT1
TXOUT2
TXOUT0 and TXOUT3 pairs at high
impedance.
TXCLK
Odd Output
Tag
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
(CH2 Data)
(CH1 Data)
Even Output
Tag
tDSO
tDSE
tDOD
31
LM98640QML-SP
www.ti.com
SNAS461G – MAY 2010 – REVISED NOVEMBER 2018
Product Folder Links: LM98640QML-SP
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Figure 24. Dual Lane LVDS Output Timing Diagram
7.3.6.3.2
Output Mode 2 - Quad Lane
In Quad Lane mode each input channel is split into two data lanes which are presented at 8x the pixel rate. The
MSBs (bits 13 through 7) will be presented to one channel while the LSBs (bits 6 through 0) will be presented to
the other. A frame signal is run at the pixel clock rate with the rising edge coincident with the transition of the
MSB of the data and the falling edge coincident with the transition of bits 10 and 3 of the data lanes for an odd
output value, and coincident with the transition of bits 11 and 4 for a even output value. A differential clock is also
output with rising edge transitions aligned within each data eye. Data rates for Quad Lane mode range from 40
Mbps, with a 5-MHz clock, up to 320 Mbps, with a 40-MHz clock.
Figure 25. Quad Lane LVDS Data Output Timing Diagram



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