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LM98640CVAL Scheda tecnica(PDF) 38 Page - Texas Instruments |
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LM98640CVAL Scheda tecnica(HTML) 38 Page - Texas Instruments |
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38 / 55 page ![]() 38 LM98640QML-SP SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 www.ti.com Product Folder Links: LM98640QML-SP Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated 7.6.1 Register Definitions NOTE: Registers need to be written with baseline values after power-up to place part in a valid state. Table 6. Register Definitions - Analog Configuration ADDRESS (BINARY) REGISTER TITLE BASELINE (BINARY) BIT(s) DESCRIPTION 00 0000 Main Configuration 0000 0100 [7:0] Main Configuration [7] Not Used [6] Coarse DAC Enable 0 Disable 1 Enable [5] Fine DAC Enable 0 Disable 1 Enable [4] Reserved [3] CLPIN Gating Enable 0 CLPIN not gated by CLAMP 1 CLPIN gated by CLAMP (=logical "and" of CLPIN and CLAMP) [2] Gain Mode Select. Selects either a 1x or 2x gain mode in the CDS/Sample/Hold Block 0 1x Gain in the CDS/Sample/Hold Block 1 2x Gain in the CDS/Sample/Hold Block [1] Reserved. Set to 0. [0] CDS / Sample/Hold Mode select. 0 Disabled. Correlated Double Sample Mode disabled. 1 Enabled. Correlated Double Sample Mode enabled. |
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