LM98640CVAL datasheet(9/55 Pages) TI2

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LM98640QML-SP

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SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

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(1)

The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided

the current is limited per Note 2 under the LM98640QML-SP Electrical Characteristics(1)(2). However, input errors will be generated If the

input goes above VDD33 and below VSS.

(2)

When the input voltage (VIN) at any pin exceeds the power supplies (VIN < VSS or VIN > VDD33), the current at that pin should be

limited to 25 mA. The 50-mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the

power supplies with an input current of 25 mA to two.

(3)

Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

6.6 LM98640QML-SP Electrical Characteristics

(1) (2)

The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 40 MHz unless otherwise

specified.

PARAMETER

TEST CONDITIONS

NOTES

SUB-

GROUPS

MIN TYP(3)

MAX UNIT

CMOS DIGITAL INPUT DC SPECIFICATIONS (SCLK, SEN, SDI, CLPIN)

VIH

Logical “1” Input Voltage

1, 2, 3

2.0

VIL

Logical “0” Input Voltage

1, 2, 3

0.8

IIH

Logical “1” Input Current

VIH = VDD33

CLPIN

1, 2, 3

100

μA

SCLK, SDI

300

SEN

0.2

μA

IIL

Logical “0” Input Current

VIL = VSS

CLPIN

1, 2, 3

–300

–85

SCLK, SDI

–300

–50

SEN

–100

–70

μA

CMOS DIGITAL OUTPUT DC SPECIFICATIONS (SDO)

VOH

Logical "1" Output Voltage

IOUT = –0.5 mA

1, 2, 3

1.8

1.93

VOL

Logical "0" Output Voltage

IOUT = 1.6 mA

1, 2, 3

0.05

0.2

IOH

Output Leakage Current

VOUT = VDD

1, 2, 3

IOL

Output Leakage Current

VOUT = VSS

1, 2, 3

–50

–20

LVDS CLOCK RECEIVER DC SPECIFICATIONS (INCLK+ and INCLK– Pins)

VIHL

Differential LVDS Clock

RL = 100 Ω

1, 2, 3

100

250

High Threshold Voltage

VCM (LVDS Input Common

Mode Voltage) = 1.25 V

VILL

Differential LVDS Clock

RL = 100 Ω

1, 2, 3

–250

–100

Low Threshold Voltage

VCM (LVDS Input Common

Mode Voltage) = 1.25 V

IIHL

Differential LVDS Clock Input

Current

VIH = VDD33

1, 2, 3

100

μA

IILL

Differential LVDS Clock Input

Current

VIL = VSS

1, 2, 3

–49

–34

μA

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