LM98640CVAL datasheet(44/55 Pages) TI2

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LM98640QML-SP

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

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Table 9. Register Definitions - Digital Configuration

ADDRESS

(BINARY)

TITLE

BASELINE

(BINARY)

BIT(s)

DESCRIPTION

11 0000

Test Pattern Start

0000 0000

[15:8]

Upper 8 bits of the Test Pattern start value. Specifies the number of

pixels after the leading edge of CLPIN to the Valid Pixel region.

11 0001

Test Pattern Start

0000 0000

[7:0]

Lower 8 bits of the Test Pattern start value. Specifies the number of

pixels after the leading edge of CLPIN to the Valid Pixel region.

11 0010

Test Pattern Width

0000 0000

[15:8]

Upper 8 bits of the Test Pattern Width value. Specifies, in number of

pixels, the width of the Valid Pixel region.

11 0011

Test Pattern Width

0000 0000

[7:0]

Lower 8 bits of the Test Pattern Width value. Specifies, in number of

pixels, the width of the Valid Pixel region.

11 0100

Test Pattern Control

0000 0000

[7:0]

Test Pattern Control Register.

[7]

Programmable Pattern Switch

0 Disabled. Normal LVDS output operation.

1 Enabled. AFE outputs LVDS test patterns.

[6:4]

Test Pattern Mode

000 Fixed Code

001 Horizontal Gradient Scan (Main Scan)

010 Vertical Gradient Scan (Sub Scan)

011 Grid Scan (Lattice Pattern)

100 Strip Pattern

101 LVDS Test Pattern. (Synchronous to CLPIN)

110 LVDS Test Pattern. (Asynchronous)

111 Not Used.

[3]

Pseudo Random Pattern Enable.

Overrides Programmable Patter Switch setting (bit 7). Normally only

one should be on.

[2]

Load Seed Enable.

When set, the seed value in the Test Pattern Value Register is loaded

in the LFSR at the leading edge of CLPIN.

[1:0]

Test Pattern Output Channel Select.

00 Both Channels

01 Channel 1

10 Channel 2

11 Not Used

11 0101

Test Pattern Pitch

0000 0000

[7:0]

Test Pattern pitch, specifies number of pixels for H Gradient pattern

and Stripe pattern, or number of lines in the V Gradient pattern, or

specifies pixels & lines in the Lattice pattern.

11 0110

Test Pattern Step

0000 0000

[7:0]

Test Pattern Step Code. Specifies step size in LSB codes the pattern is

incremented in H Gradient and V Gradient pattern. In Lattice and Stripe

pattern it specifies the code during the lower step.

11 0111

Test Pattern Channel

Offset

0000 0000

[7:0]

Test Pattern Channel Offset Register.

[7:4]

Not Used.

[3:0]

Test Pattern Channel Offset. This specifies the number of lines the

pattern on Channel 2 is delayed from Channel 1. This offset is

maintained throughout the pattern.

11 1000

Test Pattern Value

0000 0000

[15:8]

Upper 8 bits of Test Pattern Value Register. Specifies the upper 8 bits

of the test value code during Fixed Pattern and LVDS test, initial value

during H Gradient & V Gradient pattern, and higher value in the Lattice

and Stripe Pattern.

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