LM98640CVAL datasheet(24/55 Pages) TI2

24 / 55 page

INCLK (Pixel Rate)

Ideal

Pixel output from CCD

Internal Clock

(64 selectable

positions)

CLAMP

(internal pixel reference

level sampling clock)

SAMPLE

(internal pixel video

level sampling clock)

0x3F

0x1F

0x00

0x1F

Clamp Start = 0x04

Clamp End = 0x18

Sample Start = 0x25

Sample End = 0x3A

Delayed

Pixel output from CCD

CLAMP

(internal pixel reference

level sampling clock)

SAMPLE

(internal pixel video

level sampling clock)

Clamp Start = 0x1C

Clamp End = 0x32

Sample Start = 0x3E

Sample End = 0x12

Internal Clock Delay = 6.0ns + 3/64 * TINCLK

TINCLK

LM98640QML-SP

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

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Product Folder Links: LM98640QML-SP

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Feature Description (continued)

Figure 16. CDS Mode CLAMP/SAMPLE Adjust

7.3.2 Input Bias and Clamping

The inputs to the LM98640QML-SP are typically AC coupled in Correlated Double Sampling Mode (CDS Mode)

because of the switching between two signals. In Sample and Hold Mode (S/H Mode), DC coupling or AC

coupling is possible depending on the signal type. The circuit of Figure 17 shows the input structure of the

LM98640QML-SP. The DC bias point for the LM98640QML-SP side of the AC coupling capacitor can to be set

using an external DC bias resistor network, by using the CLPIN configuration, or by using the BITCLP

configuration. A typical CCD waveform is shown in Figure 18. Also shown in Figure 18 is an internal signal

“CLAMP” which can be used to “gate” the CLPIN signal so that it only occurs during the “pedestal” portion of the

CCD pixel waveform.

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