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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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LM98640CVAL Scheda tecnica(PDF) 11 Page - Texas Instruments |
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LM98640CVAL Scheda tecnica(HTML) 11 Page - Texas Instruments |
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11 / 55 page  11 LM98640QML-SP www.ti.com SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 Product Folder Links: LM98640QML-SP Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated LM98640QML-SP Electrical Characteristics (1)(2) (continued) The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 40 MHz unless otherwise specified. PARAMETER TEST CONDITIONS NOTES SUB- GROUPS MIN TYP(3) MAX UNIT POWER SUPPLY SPECIFICATIONS (see Power Trimming section for PGA and ADC Power Trimming register settings) IA VDD33 Analog Supply Current Dual Channel Power optimized for PGA Gain = 1-4x Powerdown Control Reg = 0x00 5 MHz 1, 2, 3 51.5 58 mA 15 MHz 61.3 25 MHz 69.6 40 MHz 1, 2, 3 87.6 98 VDD33 Analog Supply Current Dual Channel Power optimized for PGA Gain = 1-8x Powerdown Control Reg = 0x00 5 MHz 1, 2, 3 51.5 58 mA 15 MHz 61.3 25 MHz 72.9 40 MHz 1, 2, 3 91.3 103 VDD33 Analog Supply Current Single Channel Power optimized for PGA Gain = 1-4x Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) 5 MHz 1, 2, 3 29.5 35 mA 15 MHz 36.1 25 MHz 42 40 MHz 1, 2, 3 53.7 60 VDD33 Analog Supply Current Single Channel Power optimized for PGA Gain = 1-8x Powerdown Control Reg = 0x15 (CH1 PD) or = 0x2A (CH2 PD) 5 MHz 1, 2, 3 29.5 35 mA 15 MHz 36.1 25 MHz 43.8 40 MHz 1, 2, 3 55.6 64 VDD33 Analog Supply Current Powerdown Powerdown Control Reg = 0x80 1, 2, 3 2.85 3.85 mA ID VDD18 Digital Supply Current LVDS Quad Lane Mode LVDS Output Mode Reg = 0x0E 5 MHz 36 mA 15 MHz 39 25 MHz 42 40 MHz 45 VDD18 Digital Supply Current 5 MHz 1, 2, 3 23.5 29 mA 15 MHz 25.5 25 MHz 27.5 40 MHz 1, 2, 3 30.5 37 VDD18 Digital Supply Current Powerdown Powerdown Control Reg = 0x80 1, 2, 3 1.2 3.0 mA PWR Average Power Dissipation Power optimized for PGA Gain = 1-4x Dual Channel LVDS Dual Lane Mode 5 MHz 1, 2, 3 212 244 mW 15 MHz 250 25 MHz 280 40 MHz 1, 2, 3 345 390 Average Power Dissipation Power optimized for PGA Gain = 1-8x Dual Channel LVDS Dual Lane Mode 5 MHz 1, 2, 3 212 244 mW 15 MHz 250 25 MHz 290 40 MHz 1, 2, 3 356 407 |
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