H8SSLASH2214 datasheet(501/936 Pages) RENESAS

501 / 936 page

Section 11 Watchdog Timer (WDT)

Rev.4.00 Sep. 18, 2008 Page 441 of 872

REJ09B0189-0400

Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF

to H'00.

Bit 7

OVF

Description

[Clearing condition]

• Read TCSR* when OVF = 1, then write 0 in OVFA

(Initial value)

[Setting condition]

• When TCNT overflows (changes from H'FF to H'00)

When internal reset request generation is selected in watchdog timer mode, OVF

is cleared automatically by the internal reset.

Note: * When the interval timer interrupt is disabled and OVF is polled, read the state of OVF = 1

twice or more.

Bit 6—Timer Mode Select (WT/

IT): Selects whether the WDT is used as a watchdog timer or

interval timer. If WDT is used in watchdog timer mode, it can generate a reset when TCNT

overflows. If WDT is used in interval timer mode, it generates a WOVI interrupt request to the

CPU when TCNT overflows.

Bit 6

WT/

Description

Interval timer mode: Interval timer interrupt (WOVI) request is sent to

CPU when TCNT overflows

(Initial value)

Watchdog timer mode: Internal reset can be selected when TCNT overflows*

Note: * For details of the case where TCNT overflows in watchdog timer mode, see section

11.2.3, Reset Control/Status Register (RSTCSR).

Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.

Bit 5

TME

Description

TCNT is initialized to H'00 and count operation is halted

(Initial value)

TCNT counts

WDT0 TCSR bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.

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