H8SSLASH2214 datasheet(502/936 Pages) RENESAS

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Section 11 Watchdog Timer (WDT)

Rev.4.00 Sep. 18, 2008 Page 442 of 872

REJ09B0189-0400

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,

obtained by dividing the system clock (

φ) for input to TCNT.

Bit 2

Bit 1

Bit 0

Description

CKS2

CKS1

CKS0

Clock

Overflow Period* (when

φ = 10 MHz)

φ/2 (Initial value)

51.2 µs

φ/64

1.6 ms

φ/128

3.2 ms

φ/512

13.2 ms

φ/2048

52.4 ms

φ/8192

209.8 ms

φ/32768

838.8 ms

φ/131072

3.36 s

Note: * The overflow period is the time from when TCNT starts counting up from H'00 until

overflow occurs.

11.2.3

Reset Control/Status Register (RSTCSR)

WOVF

R/(W)*

RSTE

R/W

RSTS

R/W

—

Bit

Initial value :

R/W

Note: * Only 0 can be written, to clear the flag.

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal.

RSTCSR is initialized to H'1F by a reset signal from the

RES pin, but not by the internal reset

signal caused by a WDT overflow.

Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details

see section 11.2.4, Notes on Register Access.

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