H8SSLASH2214 datasheet(629/936 Pages) RENESAS

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Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 569 of 872

REJ09B0189-0400

• Before branching to the programming control program (RAM area H'FFC000), the chip

terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE

and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data

output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1).

The contents of the CPU’s internal general registers are undefined at this time, so these

registers must be initialized immediately after branching to the programming control program.

In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area

must be specified for use by the programming control program.

Initial settings must also be made for all other on-chip registers.

• Boot mode can be entered by making the pin settings shown in table 15.8 and executing a

reset-start.

Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting

the FWE pin and mode pins, and executing reset release*

1. Boot mode can also be cleared by a

WDT overflow reset.

Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low

while the boot program is being executed or while flash memory is being programmed or

erased*

• If the mode pin input levels are changed (for example, from low to high) during a reset, the

state of ports with multiplexed address functions and bus control output pins (

AS, RD, HWR)

will change according to the change in the microcomputer’s operating mode*

Therefore, care must be taken to make pin settings to prevent these pins from becoming output

signal pins during a reset, or to prevent collision with signals outside the microcomputer.

Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t

MDS =

200 ns) with respect to the reset release timing.

2. For further information on FWE application and disconnection, see section 15.15,

Flash Memory Programming and Erasing Precautions.

3. See appendix D, Pin States.

15.8.2

User Program Mode

When set to user program mode, the chip can program and erase its flash memory by executing a

user program/erase control program. Therefore, on-board reprogramming of the on-chip flash

memory can be carried out by providing on-board means of FWE control and supply of

programming data, and storing a program/erase control program in part of the program area as

necessary.

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