| Motore di ricerca datesheet componenti elettronici |
|
H8S/2214 Scheda tecnica(PDF) 632 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8S/2214 Scheda tecnica(HTML) 632 Page - Renesas Technology Corp |
|
632 / 936 page ![]() Section 15 ROM Rev.4.00 Sep. 18, 2008 Page 572 of 872 REJ09B0189-0400 Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (t spsu + tsp200 + tcp + tcpsu) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of tspsu µs or more, the operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during which the P1 bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 15.9.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P1 bit in FLMCR1 is cleared, then the PSU1 bit is cleared at least t cp µs later). The watchdog timer is cleared after the elapse of t cpsu µs or more, and the operating mode is switched to program-verify mode by setting the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of t spv µs or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least t spvr µs after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 15.14) and transferred to the reprogram data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least t cpv µs, then clear the SWE1 bit in FLMCR1 to 0. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |