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H8S/2214 Scheda tecnica(PDF) 665 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 665 Page - Renesas Technology Corp |
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665 / 936 page ![]() Section 16 Clock Pulse Generator Rev.4.00 Sep. 18, 2008 Page 605 of 872 REJ09B0189-0400 Section 16 Clock Pulse Generator 16.1 Overview The H8S/2214 Group has an on-chip clock pulse generator (CPG) that generates the system clock ( φ), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, duty adjustment circuit, medium- speed clock divider, and bus master clock selection circuit. 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the clock pulse generator. Legend: LPWRCR: SCKCR: Low-power control register System clock control register EXTAL XTAL Duty adjustment circuit Medium- speed clock divider System clock oscillator System clock to φ pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC φ/2 to φ/32 φ SCK2 to SCK0 SCKCR RFCUT LPWRCR Bus master clock selection circuit Figure 16.1 Block Diagram of Clock Pulse Generator |
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