H8SSLASH2214 datasheet(666/936 Pages) RENESAS

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Section 16 Clock Pulse Generator

Rev.4.00 Sep. 18, 2008 Page 606 of 872

REJ09B0189-0400

16.1.2

The clock pulse generator is controlled by SCKCR and LPWRCR. Table 16.1 shows the register

configuration.

Table 16.1

Clock Pulse Generator Register

Name

Abbreviation

R/W

Initial Value

Address*

System clock control register

SCKCR

R/W

H'00

H'FDE6

Low-power control register

LPWRCR

R/W

H'00

H'FDEC

Note: * Lower 16 bits of the address.

16.2

16.2.1

System Clock Control Register (SCKCR)

PSTOP

R/W

—

R/W

—

R/W

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs

φ clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—

φ Clock Output Disable (PSTOP): Controls φ output.

Description

Bit 7

High–Speed Mode

Software Standby

Hardware

PSTOP

Medium-Speed Mode

Sleep Mode

Mode, Watch

Standby Mode

φ output (initial value)

φ output

Fixed high

High impedance

Fixed high

High impedance

Bits 6 and 3—Reserved: This bit can be read or written to, but only 0 should be written.

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