H8SSLASH2214 datasheet(667/936 Pages) RENESAS

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Section 16 Clock Pulse Generator

Rev.4.00 Sep. 18, 2008 Page 607 of 872

REJ09B0189-0400

Bits 5 and 4—Reserved: Read-only bits, always read as 0.

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock

used in high-speed mode and medium-speed mode.

Bit 2

Bit 1

Bit 0

SCK2

SCK1

SCK0

Description

Bus master is in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

—

16.2.2

Low-Power Control Register (LPWRCR)

—

R/W

—

R/W

—

R/W

—

R/W

RFCUT

R/W

STC0

R/W

—

R/W

STC1

R/W

Bit

Initial value :

R/W

LPWRCR is an 8-bit readable/writable register that performs power-down mode control.

LPWRCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not

initialized by a manual reset or in software standby mode.

Bits 7 to 4—Reserved: These bits can be read or written to, but only 0 should be written.

Bit 3—On-chip Feedback Resistor Control (RFCUT): Selects whether the oscillator’s on-chip

feedback resistor and duty adjustment circuit are used with external clock input. Do not access this

bit when a crystal oscillator is used.

After this bit is set when using external clock input, a transition should intially be made to

software standby mode. Switching between use and non-use of the oscillator’s on-chip feedback

resistor and duty adjustment circuit is performed when the transition is made to software standby

mode.

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