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H8S/2214 Scheda tecnica(PDF) 810 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 810 Page - Renesas Technology Corp |
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810 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 750 of 872 REJ09B0189-0400 SCKCR—System Clock Control Register H'FDE6 Clock Pulse Generator 7 PSTOP 0 R/W 6 — 0 R/W 5 — 0 — 4 — 0 — 3 — 0 R/W 0 SCK0 0 R/W 2 SCK2 0 R/W 1 SCK1 0 R/W Bit Initial value R/W : : : φ Clock Output Disable 0 1 φ output Fixed high φ output Fixed high Fixed high Fixed high High impedance High impedance System Clock Select 2 to 0 0 1 0 1 0 1 0 1 0 1 0 1 — Bus master is in high-speed mode Medium-speed clock is φ/2 Medium-speed clock is φ/4 Medium-speed clock is φ/8 Medium-speed clock is φ/16 Medium-speed clock is φ/32 — Reserved Only 0 should be written to this bit. Reserved Only 0 should be written to this bit. Hardware Standby Mode Software Standby Mode Sleep Mode High-Speed Mode, Medium-Speed Mode PSTOP MDCR—Mode Control Register H'FDE7 MCU 7 — 1 — 6 — 0 — 5 — 0 — 4 — 0 — 3 — 0 — 0 MDS0 —* R 2 MDS2 —* R 1 MDS1 —* R Note: * Determined by pins MD2 to MD0. Bit Initial value R/W : : : These bits correspond to the mode pins (MD2 to MD0). When MDCR is read, the input levels at the mode pins (MD2 to MD0) are latched in bits MDS2 to MDS0. Mode Select 2 to 0 |
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