H8SSLASH2214 datasheet(812/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 752 of 872

REJ09B0189-0400

PFCR—Pin Function Control Register

H'FDEB

Bus Controller

—

R/W

—

R/W

—

R/W

—

R/W

AE3

R/W

AE0

R/W

AE2

R/W

AE1

R/W

Bit

Modes 4 and 5

Initial value

Modes 6 and 7

Initial value

R/W

Address Output Enable 3 to 0

A8 to A23 output disabled

A8 output enabled; A9 to A23 output disabled

A8, A9 output enabled; A10 to A23 output disabled

A8 to A10 output enabled; A11 to A23 output disabled

A8 to A11 output enabled; A12 to A23 output disabled

A8 to A12 output enabled; A13 to A23 output disabled

A8 to A13 output enabled; A14 to A23 output disabled

A8 to A14 output enabled; A15 to A23 output disabled

A8 to A15 output enabled; A16 to A23 output disabled

A8 to A16 output enabled; A17 to A23 output disabled

A8 to A17 output enabled; A18 to A23 output disabled

A8 to A18 output enabled; A19 to A23 output disabled

A8 to A19 output enabled; A20 to A23 output disabled

A8 to A20 output enabled; A21 to A23 output disabled

A8 to A21 output enabled; A22, A23 output disabled

A8 to A23 output enabled

Note: In expanded mode with on-chip ROM enabled, address pins A0 to A7 are made address

outputs by setting the corresponding DDR bits to 1; in expanded mode with on-chip ROM

disabled, address pins A0 to A7 are always address outputs.

Reserved

Only 0 should be written to these bits.

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