H8SSLASH2214 datasheet(855/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 795 of 872

REJ09B0189-0400

TSR2—Timer Status Register 2

H'FF35

TPU2

TCFD

—

TCFU

R/(W)*

TCFV

R/(W)*

—

TGFA

R/(W)*

—

TGFB

R/(W)*

Bit

Initial value

R/W

Note: * Can only be written with 0 for flag clearing.

Input Capture/Output Compare Flag A

[Clearing conditions]

• When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0

• When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in

DMAC is 1

• When 0 is written to TGFA after reading TGFA = 1

[Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output compare register

• When TCNT value is transferred to TGRA by input capture signal

while TGRA is functioning as input capture register

Input Capture/Output Compare Flag B

[Clearing conditions]

• When DTC is activated by TGIB interrupt while DISEL bit of MRB

in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

[Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare

• When TCNT value is transferred to TGRB by input capture signal

while TGRB is functioning as input capture register

Overflow Flag

[Clearing condition]

• When 0 is written to TCFV after reading TCFV = 1

[Setting condition]

• When the TCNT value overflows (changes from H'FFFF to H'0000 )

Underflow Flag

[Clearing condition]

• When 0 is written to TCFU after reading TCFU = 1

[Setting condition]

• When the TCNT value underflows (changes from H'0000 to H'FFFF)

Count Direction Flag

TCNT counts down

TCNT counts up

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