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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 358 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 358 Page - Renesas Technology Corp |
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358 / 1071 page  Section 8 DMA Controller (DMAC) Rev. 5.00 Aug 08, 2006 page 272 of 982 REJ09B0054-0500 DMA read DMA write DMA read DMA write DMA read DMA write DMA read φ Address bus RD HWR LWR DMA control Channel 0A Channel 0B Channel 1 Idle Write Idle Read Write Idle Read Write Read Request hold Request hold Bus release Channel 0A transfer Bus release Channel 0B transfer Channel 1 transfer Bus release Request hold Read Selection Non- selection Selection Request clear Request clear Request clear Figure 8.33 Example of Multi-Channel Transfer 8.5.12 Relation between DMAC and External Bus Requests, and DTC The DMA read cycle and write cycle are inseparable, and so the external bus release cycle and DTC cycle do not arise between the DMA external read cycle and internal write cycle. When the read cycle and write cycle are set in series as in a burst transfer or block transfer, the external bus release may be inserted after the write cycle. As the DTC has a lower priority than the DMAC, it is not executed until the DMAC releases the bus. When the DMA read cycle or write cycle accesses the on-chip memory or an internal I/O register, the DMAC cycle or external bus release may be executed at the same time. 8.5.13 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. |
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