H8SSLASH2224 datasheet(357/1071 Pages) RENESAS

357 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 271 of 982

REJ09B0054-0500

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the

DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the

request is cleared. After the end of the single cycle, acceptance resumes,

DREQ pin low level

sampling is performed again, and this operation is repeated until the transfer ends.

8.5.11

Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table

8.11 summarizes the priority order for DMAC channels.

Table 8.11 DMAC Channel Priority Order

Short Address Mode

Full Address Mode

Priority

Channel 0A

Channel 0

High

Channel 0B

Channel 1A

Channel 1

Channel 1B

Low

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for

another channel is issued during a transfer, when the bus is released, the DMAC selects the

highest-priority channel from among those issuing a request according to the priority order shown

in table 8.11. During burst transfer, or when one block is being transferred in block transfer, the

channel will not be changed until the end of the transfer. Figure 8.33 shows a transfer example in

which transfer requests are issued simultaneously for channels 0A, 0B, and 1.

H8S/2224 Scheda tecnica(PDF) 357 Page - Renesas Technology Corp