H8SSLASH2224 datasheet(356/1071 Pages) RENESAS

356 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 270 of 982

REJ09B0054-0500

resumes after the end of the single cycle,

DREQ pin low level sampling is performed again, and

this operation is repeated until the transfer ends.

DREQ

DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel

for which the

DREQ pin is selected.

Figure 8.32 shows an example of single address mode transfer activated by the

DREQ pin low

level.

DREQ

Bus release

DMA single

Address bus

DMA control

Channel

[2]

DACK

Transfer source/

destination

Idle

[1]

[3]

[5]

[4]

[6]

[7]

Acceptance resumes

Bus release

DMA single

Bus

release

Transfer source/

destination

Request

Request clear

period

Request clear

period

Single

Minimum of

2 cycles

Minimum of

2 cycles

[1]

Acceptance after transfer enabling; the

DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] The DMAC cycle is started.

[4] [7] Acceptance is resumed after the single cycle is completed.

(As in [1], the

DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 8.32 Example of

DREQ

DREQ Pin Low Level Activated Single Address Mode Transfer

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