H8SSLASH2224 datasheet(365/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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365 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 279 of 982

REJ09B0054-0500

8.7.7

Channel Re-Setting

To reactivate a number of channels when multiple channels are enabled, use exclusive handling of

transfer end interrupts, and perform DMABCR control bit operations exclusively.

Note, in particular, that in cases where multiple interrupts are generated between reading and

writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the

DMABCR write data in the original interrupt handling routine will be incorrect, and the write may

invalidate the results of the operations by the multiple interrupts. Ensure that overlapping

DMABCR operations are not performed by multiple interrupts, and that there is no separation

between read and write operations by the use of a bit-manipulation instruction.

Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must

first be read while cleared to 0 before the CPU can write 1 to them.

H8S/2224 Scheda tecnica(PDF) 365 Page - Renesas Technology Corp