H8SSLASH2224 datasheet(364/1071 Pages) RENESAS

364 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 278 of 982

REJ09B0054-0500

In medium-speed mode, the

DREQ pin is sampled at the rising edge of the medium clock.

8.7.4

Activation by Falling Edge on

DREQ

DREQ Pin

DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.

The operation is as follows:

[1] Activation request wait state: Waits for detection of a low level on the

DREQ pin, and

switches to [2].

[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].

[3] Activation request disabled state: Waits for detection of a high level on the

DREQ pin, and

switches to [1].

After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is

enabled is performed on detection of a low level.

8.7.5

Activation Source Acceptance

At the start of activation source acceptance, a low level is detected in both

DREQ pin falling edge

sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is

detected. Therefore, a request is accepted from an internal interrupt or

DREQ pin low level that

occurs before write to DMABCRL to enable transfer.

When the DMAC is activated, take any necessary steps to prevent an internal interrupt or

DREQ

pin low level remaining from the end of the previous transfer, etc.

8.7.6

Internal Interrupt after End of Transfer

When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible

termination, the selected internal interrupt request will be sent to the CPU or DTC even if the DTA

bit in DMABCRH is set to 1.

Also, if internal DMAC activation has already been initiated when operation is forcibly

terminated, the transfer is executed but flag clearing is not performed for the selected internal

interrupt even if the DTA bit is set to 1.

An internal interrupt request following the end of transfer or a forcible termination should be

handled by the CPU as necessary.

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