H8SSLASH2224 datasheet(361/1071 Pages) RENESAS

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Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 275 of 982

REJ09B0054-0500

8.6

Interrupt Sources

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 8.12

shows the interrupt sources and their priority order.

Table 8.12 Interrupt Sources and Priority Order

Interrupt

Interrupt Source

Interrupt

Name

Short Address Mode

Full Address Mode

Priority Order

DEND0A

Interrupt due to end of

transfer on channel 0A

Interrupt due to end of

transfer on channel 0

High

DEND0B

Interrupt due to end of

transfer on channel 0B

Interrupt due to break in

transfer on channel 0

DEND1A

Interrupt due to end of

transfer on channel 1A

Interrupt due to end of

transfer on channel 1

DEND1B

Interrupt due to end of

transfer on channel 1B

Interrupt due to break in

transfer on channel 1

Low

Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for

the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt

controller independently. The priority of transfer end interrupts on each channel is decided by the

interrupt controller, as shown in table 8.12.

Figure 8.37 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is

always generated when the DTIE bit is set to 1 while the DTE bit in DMABCRL is cleared to 0.

DTE/

DTME

DTIE

Transfer end/transfer

break interrupt

Figure 8.37 Block Diagram of Transfer End/Transfer Break Interrupt

In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0

while the DTIE bit is set to 1. In both short address mode and full address mode, DMABCR

should be set so as to prevent the occurrence of a combination that constitutes a condition for

interrupt generation during setting.

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