H8SSLASH2224 datasheet(363/1071 Pages) RENESAS

363 / 1071 page

Section 8 DMA Controller (DMAC)

Rev. 5.00 Aug 08, 2006 page 277 of 982

REJ09B0054-0500

• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC

[1]

[2]

Note: The lower word of MAR is the updated value after the operation in [1].

CPU longword read

DMA transfer cycle

MAR upper

word read

MAR lower

word read

DMA read

DMA write

DMA internal

address

DMA control

DMA register

operation

Transfe

source

Transfer

destination

Idle

Read

Write

Idle

Figure 8.39 Contention between DMAC Register Update and CPU Read

8.7.2

Module Stop

When the MSTPA7 bit in MSTPCRA is set to 1, the DMAC clock stops, and the module stop

state is entered. However, 1 cannot be written to the MSTPA7 bit if any of the DMAC channels is

enabled. This setting should therefore be made when DMAC operation is stopped.

When the DMAC clock stops, DMAC register accesses can no longer be made. Since the

following DMAC register settings are valid even in the module stop state, they should be

invalidated, if necessary, before a module stop.

• Transfer end/break interrupt (DTE = 0 and DTIE = 1)

• TEND pin enable (TEE = 1)

• DACK pin enable (FAE = 0 and SAE = 1)

8.7.3

Medium-Speed Mode

When the DTA bit is cleared to 0, the internal interrupt signal that is specified for the DMAC

transfer source is detected at the edge. In medium-speed mode, the DMAC operates by the

medium-speed clock and the internal peripheral module operates by the high-speed clock.

Therefore, when the corresponding interruption source is cleared by the CPU, DTC, or other

channels of the DMAC and the period until the next interruption is executed is less than one state

regarding to the DMAC clock (bus master clock), the signal is not detected at the edge and

ignored.

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