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H8S/2224 Scheda tecnica(PDF) 380 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 380 Page - Renesas Technology Corp |
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380 / 1071 page ![]() Section 9 Data Transfer Controller (DTC) Rev. 5.00 Aug 08, 2006 page 294 of 982 REJ09B0054-0500 9.5 Operation Register information is stored in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to the memory. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Figure 9.5 shows the flowchart of DTC operation. Start End Read DTC vector Read register infomation Data transfer Write register information Interrupt exception handling Clear DTCER Clear an activation flag CHNE = 1 Next transfer Yes No Yes No Transfer Counter = 0 or DISEL = 1 Note: * For details of the operation, see the section for each peripheral module. * Figure 9.5 Flowchart of DTC Operation |
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