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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 384 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 384 Page - Renesas Technology Corp |
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384 / 1071 page  Section 9 Data Transfer Controller (DTC) Rev. 5.00 Aug 08, 2006 page 298 of 982 REJ09B0054-0500 9.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the memory map for chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. DTC vector address Register information CHNE = 1 Register information CHNE = 0 Register information start address Source Destination Source Destination Figure 9.9 Chain Transfer Operation |
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