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H8S/2224 Scheda tecnica(PDF) 383 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 383 Page - Renesas Technology Corp |
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383 / 1071 page ![]() Section 9 Data Transfer Controller (DTC) Rev. 5.00 Aug 08, 2006 page 297 of 982 REJ09B0054-0500 Table 9.5 lists the register information in block transfer mode. Figure 9.8 shows the memory mapping in block transfer mode. Table 9.5 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds block size DTC transfer count register AL CRAL Designates block size count DTC transfer count register B CRB Transfer count First block Transfer Block area Nth block DAR or SAR SAR or DAR · · · Figure 9.8 Memory Mapping in Block Transfer Mode |
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