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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 381 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 381 Page - Renesas Technology Corp |
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381 / 1071 page  Section 9 Data Transfer Controller (DTC) Rev. 5.00 Aug 08, 2006 page 295 of 982 REJ09B0054-0500 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 9.3 lists the register information in normal mode. Figure 9.6 shows the memory mapping in normal mode. Table 9.3 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used SAR DAR Transfer Figure 9.6 Memory Mapping in Normal Mode 9.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. |
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