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H8S/2224 Scheda tecnica(PDF) 382 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 382 Page - Renesas Technology Corp |
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382 / 1071 page  Section 9 Data Transfer Controller (DTC) Rev. 5.00 Aug 08, 2006 page 296 of 982 REJ09B0054-0500 Table 9.4 lists the register information in repeat mode. Figure 9.7 shows the memory mapping in repeat mode. Table 9.4 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC transfer count register AL CRAL Designates transfer count DTC transfer count register B CRB Not used SAR or DAR DAR or SAR Repeat area Transfer Figure 9.7 Memory Mapping in Repeat Mode 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size can be between 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt is requested. |
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