H8SSLASH2224 datasheet(385/1071 Pages) RENESAS

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Section 9 Data Transfer Controller (DTC)

Rev. 5.00 Aug 08, 2006 page 299 of 982

REJ09B0054-0500

9.5.5

Interrupts

An interrupt request is issued to the CPU when the DTC has completed the specified number of

data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt

activation, the interrupt set as the activation source is generated. These interrupts to the CPU are

subject to CPU mask level and interrupt controller priority level control.

In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is

generated.

When the DISEL bit is 1 and one data transfer has been completed, or the specified number of

transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an

SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit

to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

9.5.6

Operation Timing

Figures 9.10 to 9.12 show the DTC operation timings.

DTC activation

request

DTC

request

Address

Vector read

Read Write

Data transfer

Transfer

information write

Transfer

information read

Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

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