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H8S/2224 Scheda tecnica(PDF) 523 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 523 Page - Renesas Technology Corp

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Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Aug 08, 2006 page 437 of 982
REJ09B0054-0500
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T1
T2
N
TGR
N
M
Buffer register write data
Figure 11.49 Contention between Buffer Register Write and Compare Match
11.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 11.50 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T1
T2
M
Internal
data bus
X
M
Figure 11.50 Contention between TGR Read and Input Capture



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