H8SSLASH2224 datasheet(526/1071 Pages) RENESAS

526 / 1071 page

Section 11 16-Bit Timer Pulse Unit (TPU)

Rev. 5.00 Aug 08, 2006 page 440 of 982

REJ09B0054-0500

11.10.12 Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, when

overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is

not set.

Figure 11.54 shows the operation timing when there is contention between TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

H'FFFF

TCNT write data

TCFV flag

Prohibited

Figure 11.54 Contention between TCNT Write and Overflow

11.10.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin

with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input

pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not

be performed from a multiplexed pin.

11.10.14 Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source or the DMAC* or DTC activation source. Interrupts should

therefore be disabled before entering module stop mode.

Note: * Supported only by the H8S/2239 Group.

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