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H8S/2224 Scheda tecnica(PDF) 522 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 522 Page - Renesas Technology Corp

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Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Aug 08, 2006 page 436 of 982
REJ09B0054-0500
11.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 11.48 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T1
T2
N
M
TGR write data
TGR
N
N + 1
Prohibited
Figure 11.48 Contention between TGR Write and Compare Match
11.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 11.49 shows the timing in this case.



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