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H8S/2224 Scheda tecnica(PDF) 524 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 524 Page - Renesas Technology Corp

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Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Aug 08, 2006 page 438 of 982
REJ09B0054-0500
11.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.51 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T1
T2
M
TGR
M
TGR address
Figure 11.51 Contention between TGR Write and Input Capture
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.52 shows the timing in this case.



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