H8SSLASH2224 datasheet(558/1071 Pages) RENESAS

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Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 472 of 982

REJ09B0054-0500

13.3.3

Reset Control/Status Register (RSTCSR) (only WDT_0)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects

the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the

RES pin,

and not by the WDT internal reset signal caused by overflows.

Bit

Bit Name

Initial

Value

R/W

Description

7WOVF

R/(W)*

Watchdog Overflow Flag

This bit is set when TCNT overflows in watchdog

timer mode. This bit cannot be set in interval timer

mode, and only 0 can be written, to clear the flag.

[Setting condition]

Set when TCNT overflows (changed from H'FF to

H'00) in watchdog timer mode

[Clearing condition]

Cleared by reading RSTCSR when WOVF = 1,

and then writing 0 to WOVF

RSTE

R/W

Reset Enable

Specifies whether or not a reset signal is

generated in the chip if TCNT overflows during

watchdog timer operation.

0: Reset signal is not generated even if TCNT

overflows (Though this LSI is not reset, TCNT

and TCSR in WDT are reset)

1: Reset signal is generated if TCNT overflows

RSTS

R/W

Reset Select

This bit selects the type of the internal reset that is

generated by TCNT overflowing in watchdog timer

mode.

0: Power-on reset

1: Manual reset

4 to 0



All 1



Reserved

These bits are always read as 1 and cannot be

modified.

Note:

* Only 0 can be written, to clear the flag.

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