H8SSLASH2224 datasheet(559/1071 Pages) RENESAS

559 / 1071 page

Section 13 Watchdog Timer (WDT)

Rev. 5.00 Aug 08, 2006 page 473 of 982

REJ09B0054-0500

13.4

Operation

13.4.1

Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/

IT bit in TCSR and the TME bit to 1.

Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00)

before overflows occurs. Thus, TCNT does not overflow while the system is operating normally.

When the WDT is used as a watchdog timer and the RSTE bit in RSTCSR of WDT_0 is set to 1,

and if TCNT overflows without being rewritten because of a system malfunction or other error, an

internal reset signal for this LSI is output for 518 system clocks.

When the RST/

NMI bit in TCSR of WDT_1 is set to 1, and if TCNT overflows, the internal reset

signal is output for 516 system clock periods. When the RST/

NMI bit is cleared to 0, an NMI

interrupt request is generated (for 515 or 516 system clock periods when the clock source is set to

φSUB (PSS = 1)).

An internal reset request from the watchdog timer and a reset input from the

RES pin are both

treated as having the same vector. If a WDT internal reset request and the

RES pin reset occur at

the same time, the

RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.

An NMI request from the watchdog timer and an interrupt request from the NMI pin are both

treated as having the same vector. So, avoid handling an NMI request from the watchdog timer

and an interrupt request from the NMI pin at the same time.

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