H8SSLASH2224 datasheet(690/1071 Pages) RENESAS

690 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 604 of 982

REJ09B0054-0500

3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock

mode has been specified, and synchronized with the input clock when use of an external clock

has been specified.

4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).

5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the

output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request

is generated. The SCK pin is fixed high.

Figure 15.20 shows a sample flow chart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.

Make sure that the receive error flags are cleared to 0 before starting transmission. Note that

clearing the RE bit to 0 does not clear the receive error flags.

Transfer direction

Bit 0

Serial data

Synchronization

clock

1 frame

TDRE

TEND

Data written to TDR

and TDRE flag cleared

to 0 in TXI interrupt

service routine

TXI interrupt

request generated

Bit 1

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

TXI interrupt

request generated

TEI interrupt request

generated

Figure 15.19 Sample SCI Transmission Operation in Clocked Synchronous Mode

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