H8SSLASH2224 datasheet(689/1071 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 603 of 982

REJ09B0054-0500

Wait

Start initialization

Set data transfer format in

SMR and SCMR

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in SCR to 1, and

set RIE, TIE, TEIE, and MPIE bits

[4]

1-bit interval elapsed?

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

[1]

[1] Set the clock selection in SCR. Be sure

to clear bits RIE, TIE, TEIE, and MPIE,

TE and RE, to 0.

[2] Set the data transfer format in SMR and

SCMR.

[3] Write a value corresponding to the bit

rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then set

the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE TEIE, and MPIE

bits.

Setting the TE and RE bits enables the

TxD and RxD pins to be used.

Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared

to 0 or set to 1 simultaneously.

Figure 15.18 Sample SCI Initialization Flowchart

15.6.3

Serial Data Transmission (Clocked Synchronous Mode)

Figure 15.19 shows an example of SCI operation for transmission in clocked synchronous mode.

In serial transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has

been written to TDR, and transfers the data from TDR to TSR.

2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt

(TXI) is generated. Continuous transmission is possible because the TXI interrupt routine

writes the next transmit data to TDR before transmission of the current transmit data has been

completed.

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