H8SSLASH2224 datasheet(733/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 647 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

SCP

Start Condition/Stop Condition Prohibit bit

The SCP bit controls the issue of start/stop conditions in

master mode.

To issue a start condition, write 1 in BBSY and 0 in SCP. A

retransmit start condition is issued in the same way. To issue

a stop condition, write 0 in BBSY and 0 in SCP. This bit is

always read as 1. If 1 is written, the data is not stored.

When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags

must be checked in order to identify the source that set IRIC to 1. Although each source has a

corresponding flag, caution is needed at the end of a transfer.

When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. Even

when data transfer is complete, the DTC activation request flag, IRTR, is not set until a

retransmission start condition or stop condition is detected after a slave address (SVA) or general

call address matched in the I2C bus format slave mode.

Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.

For a continuous transfer using the DTC, the IRIC or IRTR flag is not cleared at the completion of

the specified number of times of transfers. On the other hand, the TDRE and RDRF flags are

cleared because the specified number of times of read/write operations have been complete.

Table 16.4 shows the relationship between the flags and the transfer states.

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