H8SSLASH2224 datasheet(735/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 649 of 982

REJ09B0054-0500

16.3.7 I2C Bus Status Register (ICSR)

ICSR consists of status flags.

Bit

Bit Name

Initial

Value

R/W

Description

ESTP

R/(W)* Error Stop Condition Detection Flag

This bit is valid in I

2C bus format slave mode.

[Setting condition]

When a stop condition is detected during frame transfer

[Clearing conditions]

• When 0 is written in ESTP after reading the state of 1

• When the IRIC flag is cleared to 0

6STOP

R/(W)* Normal Stop Condition Detection Flag

This bit is valid in I

2C bus format slave mode.

[Setting condition]

When a stop condition is detected during frame transfer

[Clearing conditions]

• When 0 is written in STOP after reading STOP = 1

• When the IRIC flag is cleared to 0

IRTR

R/(W)* I

2C Bus Interface Continuous Transmission/Reception

Interrupt Request Flag

[Setting conditions]

In I

2C bus interface slave mode

• When the TDRE or RDRF flag is set to 1 when AASX = 1

In I

2C bus interface other modes

• When the TDRE or RDRF flag is set to 1

[Clearing conditions]

• When 0 is written in IRTR after reading IRTR = 1

• When the IRIC flag is cleared to 0 while ICE is 1

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