H8SSLASH2224 datasheet(739/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 653 of 982

REJ09B0054-0500

16.3.8

DDC Switch Register (DDCSWR)

DDCSWR controls the I2C bus interface format automatic switching function and internal latch

clear.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 4



All 0

R/(W)* Reserved

The write value should always be 0.

CLR3

CLR2

CLR1

CLR0

2C Bus Interface Clear 3 to 0

When bits CLR3 to CLR0 are set, a clear signal is generated

for the I

2C bus interface internal latch circuit, and the internal

state is initialized. The write data for these bits is not retained.

To perform I

2C clearance, bits CLR3 to CLR0 must be written

to simultaneously using an MOV instruction. Do not use a bit

manipulation instruction such as BCLR.

××: Setting prohibited

0100: Setting prohibited

0101: IIC_0 internal latch cleared

0110: IIC_1 internal Iatch cleared

0111: IIC_0, IIC_1 internal Iatch cleared

×××: Invalid setting

Legend:

×:

Don’t care

Note:

* Only 0 can be written to these bits, to clear the flag.

16.4

Operation

The I2C bus interface has serial and I2C bus formats.

16.4.1

I2C Bus Data Format

The I2C bus formats are addressing formats and an acknowledge bit is inserted. The first frame

following a start condition always consists of 8 bits. The I2C bus format is shown in figure 16.3.

The clocked synchronous serial format is a non-addressing format with no acknowledge bit. This

is shown in figure 16.4. Figure 16.5 shows the I2C bus timing.

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