H8SSLASH2224 datasheet(742/1071 Pages) RENESAS

742 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 656 of 982

REJ09B0054-0500

Figure 16.7 is a flowchart showing an example of the master transmit mode.

Start

Initial settings

Write BBSY = 1

and SCP = 0 (ICCR)

BBSY = 0?

Yes

[1]

Initial settings.

[2]

Determine status of SCL and SDA lines.

[3]

Set to master transmit mode.

[4]

Generate start condition.

[5]

Wait for start condition to be met.

[6]

Set 1st byte (slave address + R/

W) transmit data.

(Perform ICDR write and IRIC flag clear

operations continuously.)

[7]

Wait for end of 1 byte transmission.

[8]

Judge acknowledge signal from specified.

slave device.

[9]

Set transmit data for 2nd byte onward.

(Perform ICDR write and IRIC flag clear

operations continuously.)

[10] Wait for end of 1 byte transmission.

[11] Judge end of transmission.

[12] Generate stop condition.

Set MST = 1

and TRS = 1 (ICCR)

Read IRIC flag in ICCR

Clear IRIC flag in ICCR

Write transmit data to ICDR

Read BBSY flag in ICCR

Read ACKB bit in ICSR

IRIC = 1?

Transmit mode?

ACKB = 0?

Clear IRIC flag in ICCR

Write transmit data to ICDR

Read IRIC flag in ICCR

Read ACKB bit in ICSR

Clear IRIC flag in ICCR

Transmit complete?

(ACKB = 1?)

IRIC = 1?

Write BBSY = 0 and

SCP = 0 (ICCR)

Write ACKE = 0 (ICCR)

(Clear ACKB = 0)

End

Master receive mode

Figure 16.7 Flowchart for Master Transmit Mode (Example)

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