H8SSLASH2224 datasheet(744/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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744 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 658 of 982

REJ09B0054-0500

[5]

[7]

234

5678

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

Data 1

Slave address

Generate start

condition

Interrupt

request

Interrupt

request

Address + R/

[9] IRIC clearance

[9] ICDR write

[6] IRIC clearance

[6] ICDR write

[4] Write BBSY = 1

and SCP = 0

(generate start

condition)

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

IRIC

IRTR

ICDRT

ICDRS

User processing

Note: Do not write data

to ICDR.

Figure 16.8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)

[7]

[10]

456

Generate start

condition

SCL

(Master output)

SDA

(Master output)

SDA

(Slave output)

IRIC

IRTR

ICDR

Bit 7

Bit 0

Bit 6

Data 2

Data 1

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

[12] Write BBSY = 0

and SCP = 0

(generate stop

condition)

[12] IRIC clearance

[11] ACKB read

[9] IRIC clearance

[9] ICDR write

User processing

Figure 16.9 Example of Master Transmit Mode Stop Condition Generation Timing

(MLS = WAIT = 0)

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